NAND flash memory cells are typically arranged in a grid pattern, where each cell can store one or more bits of data (Single-Level Cell (SLC), Multi-Level Cell (MLC), Triple-Level Cell (TLC), or Quad-Level Cell (QLC)). In NAND flash memory, a page is typically the smallest unit of data that can be written to at one time. It is formed at the intersection of a wordline and the bitlines (which span across sub-blocks or tile groups). Figure 2012a shows the schematic cell layout and address assignment of 3D NAND. NAND has string Structure: Cells are connected in series to form a string.

Figure 2012a. schematic cell layout and address assignment. [1]

Figure 2012b. 3D NAND flash memory with definition of pages.

Hierarchical Structure in NAND Flash Memory:

• Cell:

  The basic unit of storage, holding a single bit of data (in SLC) or multiple bits (in MLC, TLC, QLC).

• Page:

  A collection of cells that form the smallest unit of data that can be written or read. Typically, a page might be 4 KB or 8 KB in size.

• Block:

  A larger unit that consists of multiple pages, typically ranging from 64 to 256 pages per block. It is the smallest unit that can be erased.

• Tile:

  A subsection of the NAND memory array. A tile typically includes several blocks and associated peripheral circuitry, such as wordline drivers and bitline multiplexers. Tiles are designed to optimize the efficiency and performance of the memory array.

• Plane:

  A larger organizational unit that includes multiple blocks. Typically, a NAND die is divided into multiple planes. Each plane can operate independently, which allows for parallelism and improved performance. For instance, a NAND die might have two or four planes.

• Cell → Page → Block → Plane:

  Cells are grouped into pages. Pages are grouped into blocks. Blocks are grouped into planes. Each plane contains multiple blocks and is capable of operating independently from other planes, allowing parallel operations.

A page in NAND flash memory does not have its own periphery circuitry. The periphery circuitry is shared among multiple pages and typically includes components such as:

• Page Buffers: Temporary storage areas that hold data during read and write operations.
• Sense Amplifiers: Used to read the voltage levels from the cells and determine the stored data.
• Row and Column Decoders: Circuits that select specific rows (wordlines) and columns (bitlines) for read/write operations.
• Control Logic: Manages the overall operation of the memory array, including programming, reading, and erasing sequences.

In NAND flash memory, each page has its own set of redundant bytes, which are not shared with other pages in the block:

• Example: Assume a NAND flash memory page has 2048 bytes for user data and 64 bytes for redundant data (these numbers can vary based on the specific NAND flash design).
  • Main Data Area: 2048 bytes
  • Redundant Area: 64 bytes

• Redundant Bytes Usage:
  • Page-Specific: The 64 redundant bytes in each page are used exclusively for that page's error correction, metadata, and management data.
  • Not Shared: These redundant bytes are not shared with other pages within the same block.

[1] https://electronics.stackexchange.com/.
[2] Md Raquibuzzaman , Aleksandar Milenkovic and Biswajit Ray, EXPRESS: Exploiting Energy–Accuracy Tradeoffs in 3D NAND Flash Memory for Energy-Efficient Storage, Electronics 2022, 11, 424. https://doi.org/10.3390/electronics11030424.