In DRAM, VDD is typically the supply voltage dedicated to the memory cell array. This VDD refers to the positive power supply voltage. It is the voltage applied to the drain of an N-channel MOSFET or the source of a P-channel MOSFET, and it represents the "high" voltage level in a circuit. Figure 1968a shows the schematic diagram of a conventional sensing circuit and a 1T1C DRAM array. IO* means inverted signal of IO.

This VDD voltage is crucial for the proper functioning of the DRAM cells, which store data as electrical charges in capacitors:

• Role of VDD in DRAM
  • Powering the Memory Cells: The memory cells in DRAM consist of a capacitor and a transistor. VDD provides the necessary voltage to charge the capacitors, enabling them to store data as binary values (1s and 0s).
  • Stabilizing Data Storage: The data stored in the capacitors tends to leak over time, which necessitates periodic refreshing of the charge. VDD ensures that the capacitors can be recharged to maintain data integrity.
  • Operating the Access Transistors: The access transistors in the DRAM cells require a stable voltage to function correctly. VDD supplies this voltage, allowing the transistors to control the read and write operations efficiently.

• Separate Supply for VDD

  Having a separate supply voltage for VDD offers several benefits:

  • Noise Isolation: By isolating the memory cell array's supply voltage from other parts of the DRAM circuitry, noise and voltage fluctuations from other components (such as I/O circuits) are minimized. This isolation improves the overall stability and performance of the memory cells.
  • Power Optimization: Different components within the DRAM may require different voltage levels. By providing a dedicated VDD for the memory cell array, it is possible to optimize the voltage for the specific needs of the memory cells, leading to better power efficiency.
  • Enhanced Performance: A stable and optimized VDD contributes to the reliable operation of the memory cells, which can enhance the overall performance of the DRAM. This stability is particularly important in high-speed memory operations where precise voltage control is critical.

[1] Chenghu Dai, Yixiao Lu, Wenjuan Lu, Zhiting Lin, Xiulong Wu and Chunyu Peng, Low-Power Single Bitline Load Sense Amplifier for DRAM, Electronics 2023, 12, 4024, https://doi.org/10.3390/electronics12194024.