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Defect are defined as variation in quality that may cause a
circuit failure. Defects not only lower manufacturing yield, but
also cause potential reliability problems. The defects generated during IC processes are generally
classified into two categories:
i) Global defects (see page4257). Such defects are scattered all over the wafer and are very expensive to correct. Examples of such defects are random causes, e.g. particles in the cleanroom generate
global defects.
ii) Local defects (see page4257). Such defects are generated by assignable causes, e.g., human mistakes, particles from equipment, and chemical stains. These assignable causes are
local destructive mechanisms that generate sets of aggregated
defects or local defect clusters [1]. Typically, local defect
clusters have amorphous, linear, curvilinear, or ring-shaped
patterns [2-3]. However, the local defects on a wafer tend to form several patterns simultaneously. The specific patterns of local defect clusters
reflect defect generation mechanisms. For instance, particles
from equipment and chemical stains may generate amorphous
defect clusters [4], while clusters with curvilinear patterns
may be caused by scratches. The spatial patterns of locally
clustered defects therefore contain valuable information about
defect generation mechanisms; therefore, methods for detecting
local defect clusters and identifying their spatial patterns are
highly desirable.
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Defect Detection and Classification. Code:
![Upload Files to Webpages](images3/4263a.png)
Output:
![Upload Files to Webpages](images3/4263b.png)
![Upload Files to Webpages](images3/4263d.png)
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[1] J. Y. Hwang and W. Kuo, “Model-based clustering for integrated circuits
yield enhancement,” Eur. J. Oper. Res., vol. 178, no. 1, pp. 143–153,
2007.
[2] F. L. Chen and S. F. Liu, “A neural-network approach to recognize defect
spatial pattern in semiconductor fabrication,” IEEE Trans. Semiconduct.
Manuf., vol. 13, no. 3, pp. 366–373, Aug. 2000.
[3] C. H. Wang, W. Kuo, and H. Bensmial, “Detection and classification of
defects patterns on semiconductor wafers,” IIE Trans., vol. 39, no. 12,
pp. 1059–1069, 2006.
[4] S. S. Gleason, K. W. Tobin, T. P. Karnowski, and F. Lakhani, “Rapid
yield learning through optical defect and electrical test analysis,” Proc.
SPIE-Int. Soc. Opt. Eng., vol. 3332, pp. 232–242, 1998.
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