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Many studies have assessed process variation using probe data to determine the locations of defective chips. [1-2]. However, because multiple defects on a chip result in only a single defective chip, judgments about the root causes can be made only from defective chip data. Consequently, much information is lost if the analysis is conducted using probe data for the locations of defective chips [3].

An IC-maker processes more than 10 000 wafers per day. One of the main bottlenecks is a probe test to check for the existence of wafer defects. The test checks for defect patterns and, if defects exist, checks the whole wafers. Even if a fraction of the testing time could be reduced, it would greatly improve overall productivity.

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[1] S. J. Bae, J. Y. Hwang, and W. Kuo, “Yield prediction via spatial modeling of clustered defect counts across a wafer map,” IIE Trans., vol. 39, no. 12, pp. 1073–1083, Dec. 2007.
[2] W. Taam and M. Hamada, “Detecting spatial effects from factorial experiments: An approach from integrated circuit manufacturing,” Technomet., vol. 35, no. 2, pp. 149–160, 1993.
[3] J. Y. Hwang and W. Kuo, “Model-based clustering for integrated circuits yield enhancement,” Eur. J. Oper. Res., vol. 178, no. 1, pp. 143–153, 2007.