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Yield enhancements in the integrated circuit (IC) manufacturing process today require an expensive, long and tedious physical failure analysis process to identify the root cause. On the other hand, he continuous shrinkage of process technology nodes and increasingly complicated nature of IC designs make IC manufacturing difficult, and the number of situations where yield improvement exhibits is needed significantly. As the pressure for meeting high specifications increases, the probabilities of manufacturing process-based defects appearing in the wafers also increase. Wafer defects are becoming the primary obstacles affecting product yield in IC manufacturing. Therefore, wafer map defect classification and analysis, which locates defects at early fabrication stages, has become essential.

Some new techniques geared towards efficiently identifying a single dominant defect mechanism (for instance, in an excursion wafer) by analyzing fail data collected from the production electrical test environment. Such techniques utilizes statistical hypothesis testing in novel ways to analyze logic diagnosis data along with information on physical features in the design layout and reliably identify the dominant cause for yield loss. Therefore, the dominant failing physical feature can be correctly identified.

For wafers, which suffer low yield, sorted with manufacturing scan test patterns in the early stage of a new technology node, chain diagnosis and PFA are needed. In this cases, logic diagnosis is normally used to select PFA samples for detailed experiments. [1] In fact, unique and valuable defect information can be obtained through the analysis of the chain diagnosis results. On the other hand, in such wafers, there were a large number of failed die that are caused by the defects on scan chains. Due to the low number of failed devices passing the chain test, it was necessary to focus on chain diagnosis to have a large enough population of failed samples to pin point systematic defects. Nevertheless, using scan chain diagnosis has some challenges which need to be addressed [1]:
         i) The chain diagnosis tool used to apply model-based simulation algorithms may have two issues:
           i.a) Diagnosis accuracy and resolution were not good for defects so that it cannot be modeled as a permanent chain fault model.
           i.b) Long diagnosis run time does not satisfy the requirement of running volume diagnosis.
         ii) To guarantee the PFA success rate, a good filtering system is needed to select good diagnosis results based on the number of failing chains, diagnosis resolution, and confidence score etc.
         iii) Select a correct number of dies to perform PFA in order that failure analysis for the systematic defects during manufacturing wafer test is able to ramp up yield quickly to have more focus on solving the most severe process weakness.
         iv) Study these PFA results and combine the PFA information with other methodologies to draw a conclusion about the major yield limiting factor.

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[1] Yu Huang, Brady Benware, Wu-Tung Cheng, Ting-Pu Tai, Feng-Ming Kuo and Yuan-Shih Chen, Case study of scan chain diagnosis and PFA on a low yield wafer, 2010 IEEE International Test Conference, DOI: 10.1109/TEST.2010.5699310, (2010).