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An excursion wafer refers to a wafer whose yield is lower than normal baseline level. Excursion wafers may happen due to various unavoidable reasons, for instance, changes in fabrication equipment, changes in process parameters, and so on. When this happens, it is important to quickly identify the source that is causing the yield to drop below normal and then fix the issue since yield excursion is profit killer, especially, for fabless companies. Cycle time reduction for improving excursion yield can make a significant contribution to revenue. [5] For instance, based on the cost models with assumption of 40,000 wafers per month, revenue loss across the industry per year can be reduced to 37.1 million USD if the time required to resolved excursion issues can be reduced from 60 days to 30 days. The cost function can be easily calculated by (X wafers) * (Y dollars per wafer) * (Percentage of yield loss).

In some cases, the cause of an excursion wafer can be identified based on wafer histories, analysis of process history, etc. [1-3]. In such cases, the method that is then most often used today is, to select a small number of die from an excursion wafer and then determine the defect in the die using PFA. However, this is an expensive and time consuming process. Furthermore, it can only be done for a small number of failing die which implies that the results may still not be conclusive.

Excursion wafers are most commonly caused by a single factor and the goal is to identify the dominant failing mechanism rather than identifying and ranking various systematic yield limiters. Some analysis technique [4] had been developed to allow the use of logic diagnosis results from failing die on the excursion wafer along with physical features from the design layout to identify the cause of the excursion wafer. Such method is cheaper, quicker and more accurate than the current state of art of relying on PFA techniques alone. This kind of techniques are designed to draw conclusions from a small number of failing die and take full advantage of the fact that there is a single dominant mechanism.

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[1] R. Minixhofer and D. Rathei, “Using TCAD for fast analysis of misprocessed wafers and yield excursions”, IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 2005.
[2] F. Lee and S. Smith, “Yield analysis and data management using Yield Manager”, IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 1998.
[3] G.M. Scher, “Wafer Tracking Comes of Age”, Semiconductor International, Vol. 14, No. 6, May 1991.
[4] Manish Sharma, Brady Benware, Lei Ling, David Abercrombie, Lincoln Lee, Martin Keim, Huaxing Tang, Wu-Tung Cheng and Ting-Pu Tai, Yi-Jung Chang, Reinhart Lin, Albert Man, Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data, DOI: 10.1109/TEST.2008.4700589, 2008 IEEE International Test Conference, 2008.
[5] Excursion Yield Loss and Cycle Time Reduction in Semiconductor Manufacturing, Robert C. Leachman and Shengwei Ding, IEEE TRANSACTIONS ON AUTOMATION SCIENCE AND ENGINEERING, VOL. 8, NO. 1, January 2011