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Custom AI Chips/ICs - Python and Machine Learning for Integrated Circuits - - An Online Book - |
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| Python and Machine Learning for Integrated Circuits http://www.globalsino.com/ICs/ | ||||||||
| Chapter/Index: Introduction | A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z | Appendix | ||||||||
================================================================================= To optimize the energy efficiency in the entire machine learning system, some companies have developed custom hardware accelerators like Google's Edge TPU and Apple's Neural Engine, which are highly optimized for AI and machine learning workloads. Google's Edge TPU hardware is composed of three main components of the neural node, the multiplier, the adder and the activation function. [1] Figure 3823a shows Google's Edge TPU hardware. Figures 3823a and 3823b shows the adder and pipeline in Google's Edge TPU hardware.
Figure 3823a. Adder in Google's Edge TPU hardware.
Figure 3823b. Pipeline in Google's Edge TPU hardware. Apple Neural Engine (ANE) is a collection of specialized computational cores that exist on Apple Silicon chips. The ANE is designed to execute machine/artificial intelligence functions quickly and with great efficiency. The first ANE was introduced in September 2017 as part of the Apple A11 "Bionic" chip. It consisted of two cores that could perform up to 600 billion operations per second. Figure 3823c shows Apple Neural Processor.
Figure 3823c. Apple Neural Processor. [2] Figure 3823d shows Eyeriss system architecture used in deep learning.
Figure 3823d. Eyeriss system architecture used in deep learning. [3]
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[1] Google Coral Edge TPU explained in depth, https://qengineering.eu/google-corals-tpu-explained.html.
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